Manufacture or trench-gate semiconductor devices

ABSTRACT

The manufacture of a vertical power transistor trench-gate semiconductor device in which the source regions ( 13 ) are self-aligned to the trench-gate structures ( 20,17,11 ) including the steps of forming a mask ( 61 ) on a surface ( 10   a ) of a semiconductor body ( 10 ), using the mask ( 61 ) to form the trench-gate structures ( 20,17,11 ), then using the mask ( 61 ) to form U-shaped section layers ( 62 A,  62 B) of insulating material whose base portion ( 62 B) provides a gate insulating layer on the gate material ( 11 ), then removing the mask ( 61 ) and forming spacers ( 64 ) against well-defined steps provided by the upright portions ( 62 A) of the U-shaped section layers, then using the spacers ( 64 ) to form the source regions ( 13 ).

BACKGROUND OF THE INVENTION

This invention relates to a method of manufacturing a vertical powertransistor trench-gate semiconductor device of the type having aplurality of transistor cells, each transistor cell being surrounded bya trench-gate structure comprising a trench extending into asemiconductor body with gate material in the trench and a gateinsulating layer between the trench and the gate material, and eachtransistor cell having an annular source region adjacent an upper partof the trench-gate structure and separated from a drain region by achannel-accommodating body region adjacent the trench-gate structure.The invention also relates to semiconductor devices of this typemanufactured by such a method.

DESCRIPTION OF THE RELATED ART

In a method of manufacturing a device of the above-defined type which isknown from United States patent U.S. Pat. No. 5,378,655, the methodincludes forming the source regions so as to be self-aligned to thetrench-gate structures. This self-alignment is achieved by the disclosedand taught method summarised as follows. A trench is etched through awindow in a mask on a semiconductor body. After removing the mask, gatematerial is provided in the trench and then an upper portion of the gatematerial is oxidised to form a trench-gate structure which has aninsulating cap on the gate. The insulating cap is then caused to form astep which protrudes from the adjacent semiconductor surface. A layer isthen provided over the surface structure and then etched to leave a sidewall spacer in the trench-gate step. The spacer is then used to definethe source region which is thus formed to be self-aligned to thetrench-gate structure.

By using such techniques as disclosed in U.S. Pat. No. 5,378,655, thenumber of photolithographic masking steps which require separatealignment can be reduced and compact cellular device structures can beformed.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an alternative andadvantageous method of forming the source regions self-aligned to thetrench-gate structures.

According to the present invention there is provided a method as definedin claim 1. The method is characterised by the steps of:

(a) forming on a surface of the semiconductor body a first mask of afirst material with first windows, each said first window having amid-point path coincident with a mid-point path of the location of asaid trench;

(b) providing in each first window a U-shaped section layer of aninsulating second material, the layers of second material being providedafter the trench-gate structures are formed, each layer of secondmaterial having upright portions on the side walls of the first windowand a base portion which provides a gate insulating overlayer on thegate material of a said trench-gate structure;

(c) removing the first mask and then forming spacers, each spacer havinga vertical surface which is aligned with the location of a surface of asaid upright portion of the layer of second material and each spacerhaving a horizontal base surface;

(d) using the spacers to form the annular source regions with thelateral extent of the source regions from the trench-gate structuresbeing determined by the lateral extent of the base surface of thespacers; and

(e) providing a source electrode to contact the source regions and thebody regions adjacent the source regions.

In the method of the present invention, the upright portions of theU-shaped section layers provide well-defined steps for the spacers usedto form the source regions. Also, providing a gate insulating overlayeron the gate material by means of the base portion of the U-shapedsection layers is preferable to providing this overlayer by oxidisingthe gate material, which can involve so-called bird's beak problems.Preferred features of the present invention are indicated as follows.

The trenches may be etched using a mask of said first material asdefined in claim 2 or claim 3. These mask windows may then be widened sothat the gate insulating layers have horizontal extensions on thesemiconductor body surface which remain when the first mask is removedas defined in claim 3, these horizontal extensions advantageouslyprotecting the gate insulation near the top of the trenches during thisremoval of the first mask.

As defined in claim 5, a mask of the first material may first havepreceding U-shaped section layers provided in its windows with a centralpart of the base portion of these layers being removed to provide etchwindows for the trenches after which the remainder of the precedinglayers is removed, the mask of the first material then being used forproviding the U-shaped section layers which define steps for the spacersused to form the source regions. In this way, starting from one mask, atwo-stage self-aligned process may provide well-defined narrow trenchesand then well-defined source regions.

As defined in claims 2, 4 or 7, each spacer vertical surface may bealigned with an outer surface of one of the upright portions of thesecond material. The spacers may be formed with a third material presentin the U-shaped section layers as defined in claim 8. Otherwise, thethird material may be removed before forming the spacers of aninsulating material such that further spacers are also formed againstthe inner surfaces of the upright portions and merge to cover the baseportions of the U-shaped section layers as defined in claim 9. Suchmerged spacers forming a further insulating layer on top of the gateinsulating U-cup base advantageously reduces gate-source capacitance. Incases where the spacers are formed against the U-shaped section secondlayer uprights, the first mask may be silicon dioxide and the secondlayer may be silicon nitride as defined in claim 10; in this case thehigh etch selectivity of the oxide with respect to the nitrideadvantageously assists good definition of the nitride uprights when theoxide mask is removed.

As an alternative to forming the spacers against the U-shaped sectionsecond layer uprights, the U-shaped section layers may be filled with athird material and the upright portions may be removed when the firstmask is removed so that the spacers are formed against the thirdmaterial as defined in claim 11; in this case the first mask materialand the second layer material may both be silicon dioxide.

The source regions may be formed by etching upper regions of thesemiconductor body of a suitable conductivity type using the spacers asa mask as defined in claim 13. The spacers may then be etched as definedin claim 14 to advantageously expose top surfaces as well as sidesurfaces of the source regions for improved contact by the sourceelectrode. Preferably the upper regions which are to be etched to formthe source regions are formed by dopant implantation and diffusion afterremoving the first mask as defined in claim 15. Forming these upperregions at this late stage in the process is advantageous for thermalbudget reasons.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample, with reference to the accompanying diagrammatic drawings, inwhich:

FIGS. 1A to 1F are a cross-sectional view of part of a semiconductorbody at successive stages in the manufacture of a vertical trench-gatepower transistor by an example of a method in accordance with thepresent invention, these Figures showing the manufacture of atrench-gate structure and part of a transistor cell on either side ofthe trench-gate structure;

FIG. 2 is a cross-sectional view of the semiconductor body of FIG. 1F,showing two transistor cells with surrounding trench-gate structures andshowing source and drain electrodes;

FIGS. 3B, 3C and 3E are a cross-sectional view of the semiconductor bodyat stages corresponding to those shown respectively in FIGS. 1B, 1C and1E but modified in another example in accordance with the invention;

FIGS. 4C and 4E are a cross-sectional view of the semiconductor body atstages corresponding to those shown respectively in FIGS. 3C and 3E butmodified in another example in accordance with the invention;

FIG. 5E is a cross-sectional view of the semiconductor body at a stagecorresponding to that shown in FIG. 1E but modified in another examplein accordance with the invention; and

FIGS. 6A to 6J are a cross-sectional view of the semiconductor body atsuccessive stages in another example in accordance with the invention,wherein the stages shown in FIGS. 6H, 6I and 6J correspond respectivelybut are modified with respect to the stages shown in FIGS. 3B, 3C and3E.

It should be noted that all the Figures are diagrammatic and not drawnto scale. Relative dimensions and proportions of parts of the drawingshave been shown exaggerated or reduced in size, for the sake of clarityand convenience in the drawings. The same reference signs are generallyused to refer to corresponding or similar features in different stagesof manufacture and in modified and different embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 illustrates an exemplary embodiment of a vertical trench-gatepower transistor having a plurality of transistor cells, each transistorcell being surrounded by a trench-gate structure comprising gatematerial 11 in a trench 20 and a gate insulating layer 17, and eachtransistor cell having source and drain regions 13 and 14, respectively,of a first conductivity type (n-type in this example) which areseparated by a channel-accommodating body region 15 of the oppositesecond conductivity type (i.e. p-type in this example) adjacent to thetrench-gate structure. The application of a voltage signal to the gates11 in the on-state of the device serves in known manner for inducing aconduction channel 12 in the regions 15 and for controlling current flowin each conduction channel 12 between the source and drain regions 13and 14.

The source regions 13 and adjacent body regions 15 are contacted by asource electrode 23 at the top of the device body. The region 14 may bea drain-drift region formed by an epitaxial layer of high resistivity(low doping) on a substrate region 14 a of high conductivity. Thissubstrate region 14 a may be of the same conductivity type (n-type inthis example) as the region 14 to provide a vertical MOSFET, or it maybe of opposite conductivity type (p-type in this example) to provide avertical IGBT. The substrate region 14 a is contacted at the bottommajor surface 10 b of the device body by an electrode 24, called thedrain electrode in the case of a MOSFET and called the anode electrodein the case of an IGBT.

A vertical trench-gate power transistor, with transistor cells which maybe of square, hexagonal or elongate stripe shape geometry, typicallycomprises many hundreds of parallel transistor cells between the sourceelectrode 23 and the drain electrode 24. The active cellular area of thedevice may be bounded around the periphery of the semiconductor body 10by various known peripheral termination schemes.

The device of FIG. 2 is manufactured by a method which, in overview ofFIGS. 1A to 1E includes the steps of:

forming on a surface 10 a of a semiconductor body 10 (typically ofmonocrystalline silicon) a mask 61 of a first material (preferablysilicon dioxide) with etch windows 61 a which are used to etch trenches20, see FIG. 1A;

forming trench-gate structures each comprising a trench 20 with gatematerial 11 in the trench 20 and a gate insulating layer 17 (preferablysilicon dioxide), the layer 17 having an upward extension 17 a whichforms a narrowed window 61 b in the mask 61, see FIG. 1B;

providing in each window 61 b a U-shaped section layer of an insulatingsecond material (preferably silicon nitride) having upright portions 62Aon the side walls of the window 61 b and a base portion 62B whichprovides a gate insulating overlayer, and filling the U-shaped sectionlayer with a third material 63 (typically polycrystalline silicon), seeFIG. 1C;

removing the mask 61 and the upward insulating layer extensions 17 a,and then forming p-type regions 15 suitable for body regions and n-typeregions 13 a suitable for source regions by dopant implantation anddiffusion, see FIG. 1D; and then

forming spacers 64 (typically of silicon dioxide), each spacer beingaligned with an outer surface of an upright portion 62A of a U-shapedsection layer, and then using the spacers 64 as a mask to etch theregions 13 a to form exposed annular source regions 13 and to expose thebody regions 15, see FIG. 1E.

Summarising the above-described steps, a single mask 61 is used forforming trench-gate structures 20, 17, 11 followed by a process in whichsource regions 13 and adjacent channel-accommodating body regions 15 areformed self-aligned to the trench-gate structures. The self-alignedprocess uses U-shaped section layers whose upright portions 62A providewell-defined steps for spacers 64 used to form the source regions 13 andwhose base portions 62B provide insulating overlayers on the gates 11.This process is suitable for cellular trench-gate power transistors inwhich the transistor cell pitch is relatively small, that is to say lessthan 3 μm and typically 2 μm.

Successive stages in the manufacture of the transistor cells of FIG. 2will now be described in detail with reference to FIGS. 1A to 1F.

FIG. 1A shows a monocrystalline silicon semiconductor body 10 having anupper surface 10 a. A mask 61 of a first material, in this examplesilicon dioxide, is formed at the surface 10 a by forming a continuousthick layer using known deposition techniques, for example plasmaenhanced chemical vapour deposition, and then forming etch windows 61 ain this layer using known photolithography and etching techniques. In atypical example, the layer 61 has a thickness of 0.5 μm and each window61 a has a width of 0.6 μm. A trench 20 is then formed by etching intothe semiconductor body 10 at each window 61 a, preferably using ananisotropic plasma etch.

As illustrated by FIG. 1B, a thin gate insulating layer 17, in thisexample silicon dioxide, is then formed in each trench 20 with an upwardextension 17 a which forms a narrowed window 61 b in the mask 61. Thenarrowed windows 61 b form first windows in a first mask of the firstmaterial, silicon dioxide, each window 61 b having a mid-point pathcoincident with a mid-point path of the location of a trench 20. Thelayer 17, 17 a may be formed by deposition, or by dry oxidation of thesilicon body 10, or by oxidation by wet oxide growth. Gate material 11,which may be doped polycrystalline silicon, is then deposited in thetrench 20 on the insulating layer 17, 17 a and then etched back levelwith the semiconductor body surface 10 a. Each trench 20 together withthe gate insulating layer 17 and the gate material 11 forms atrench-gate structure to surround a transistor cell.

As illustrated in FIG. 1C, a continuous thin layer 62 of an insulatingsecond material, in this example silicon nitride, is formed bydeposition on top of the mask 61 and in each window 61 b. The layer 62is conformal to the shape of the windows 61 b and provides in eachwindow 61 b a U-shaped section layer of silicon nitride having uprightportions 62A on the side walls of the window 61 b and a base portion 62Bwhich provides a gate insulating overlayer on the gate material 11 of atrench-gate structure. In the typical example, the layer 62 has athickness of 0.05 μm. A third material 63, in this examplepolycrystalline silicon, is deposited and is then etched backanisotropically, to the level of the silicon nitride layer 62 at the topof the mask 61, and fills the U-shaped section layer 62A, 62B. Thesilicon nitride layer 62 is then etched away from the top of the firstmask 61, 17 a of silicon dioxide, and then the first mask 61, 17 a isremoved by etching to leave the U-shaped section layers 62A, 62B filledby the material 63 masking the otherwise exposed upper surface 10 a ofthe semiconductor body 10 as shown in FIG. 1D.

As further illustrated in FIG. 1D, two stages of dopant ion implantationfollowed by annealing and diffusion into the semiconductor body 10 areperformed. In the first stage p-type regions 15 are formed to a suitabledepth adjacent the trench-gate structures 20, 17, 11 suitable for thechannel-accommodating body regions of the transistor cells, a suitableacceptor dopant being boron. In the second stage regions 13 a of n+conductivity type suitable for the annular source regions of thetransistor cells are formed in an upper part of the semiconductor body10, a suitable donor dopant being phosphorous or arsenic. The regions 13a are surrounded by the U-shaped section layers 62A, 62B of siliconnitride. A thin layer of silicon dioxide (not shown) may be grown on thesemiconductor body surface 10 a before the implantation stages, and thenremoved at a later stage.

A layer of silicon dioxide is then deposited and has a contoured uppersurface (not shown) above the polycrystalline silicon filler 63, thesilicon nitride upright portions 62A and the semiconductor body uppersurface 10 a. This contoured silicon dioxide layer is thenanisotropically etched to form spacers 64 as shown in FIG. 1E. Eachsilicon dioxide spacer 64 has a vertical surface 64A aligned with anouter surface of an upright portion 62A of silicon nitride, a horizontalbase surface 64B and a curved sidewall between the vertical andhorizontal surfaces 64A and 64B.

As further illustrated in FIG. 1E, annular source regions 13 are thenformed by etching the n+ regions 13 a using the spacers 64 as a mask,the lateral extent of the source regions 13 from the trench-gatestructures 20, 17, 11 being determined by the lateral extent of the basesurface 64B of the spacers 64. Etching to form the source regions 13exposes the vertical side surfaces 13A of these source regions 13 andthe adjacent upper surfaces of the body regions 15. This etching stagealso partly etches the polycrystalline filler 63 to form a reducedheight filler 63A within each U-shaped section silicon nitride layer62A, 62B.

As illustrated in FIG. 1F, the silicon dioxide spacers 64 are thenetched back to form reduced spacers 64′, and thus to expose top surfaces13B of the source regions 13, and then the silicon nitride uprightportions 62A are etched back to form a planarised surface with thereduced height filler 63A.

Referring now to FIG. 2, two transistor cells are shown with surroundingtrench-gate structures 20, 17, 11. After forming the structure shown inFIG. 1F, two and a half such structures being shown in FIG. 2, electrodematerial (for example aluminium) is deposited to provide the sourceelectrode 23. The source electrode 23 extends over the reduced fillers63A, over the reduced upright portions 62A and over the reduced spacers64, and the source electrode 23 contacts the exposed side surface 13Aand exposed top surface 13B of the annular source region 13 in eachtransistor cell and the channel-accommodating body region 15 within andadjacent the source region 13 in each transistor cell.

Referring now to FIGS. 3B, 3C and 3E, these Figures show thesemiconductor body 10 at stages corresponding to those shownrespectively in FIGS. 1B, 1C and 1E but modified as will now bedescribed.

The trench 20 shown in FIG. 3B is formed using an etch window 61 a in asilicon dioxide mask 61 as has been described with reference to FIG. 1A.The mask 61 is then etched to widen the windows 61 a so that eachwidened window 61 c as shown in FIG. 3B forms a first window in a firstmask of the first material, silicon dioxide. The gate insulating layer17 of silicon dioxide is then formed in each trench 20 and hashorizontal extensions 17 b on the surface 10 a of the semiconductor body10 within the widened first windows 61 c. Gate material 11 is thendeposited in the trench 20 on the insulating layer 17, 17 b and thenetched back level with the top surface of the insulating layerhorizontal extensions 17 b.

As illustrated in FIG. 3C a thin layer of silicon nitride 62′ isdeposited on top of the mask 61 and in each window 61 c. A U-shapedsection layer of silicon nitride is provided in each window 61 c havingupright portions 62A′ and a base portion 62B′ which provides a gateinsulating overlayer on the gate material 11, the base portion 62B′extending over the gate insulating layer horizontal extensions 17 b. Inthe same manner as has been described with reference to FIGS. 1C and 1D,a polycrystalline silicon filler 63 is provided in the U-shaped sectionlayers 62A′, 62B′, and the top of the silicon nitride layer 62′ and thenthe first silicon dioxide mask 61 are successively removed by etching.The silicon dioxide gate insulating layer horizontal extensions 17 bremain when the silicon dioxide first mask 61 is removed, thesehorizontal extensions 17 b protecting the gate insulation 17 near thetop of the trenches 20 during this removal of the first mask 61.

The method then proceeds to the structure shown in FIG. 3E in the samemanner as has been described above with reference to FIGS. 1D and 1E.That is, two stages of dopant implantation and diffusion provide ap-type channel-accommodating body region 15 and an upper n+ type regionsurrounded by the U-shaped section layers 62A′, 62B′ of silicon nitrideon top of the gate insulating layer horizontal extensions 17 b, exceptthat in this case Hi the diffusion stages laterally extend the bodyregions and the n+regions under the extensions 17 b to the trench-gatestructures. Silicon dioxide spacers 64 are formed, each with a verticalsurface aligned with an outer surface of an upright portion 62A′, andsource regions 13 are then formed by etching the n+regions using thespacers 64 as a mask. The spacers 64 will then be reduced to expose topsurfaces of the source regions 13 shown in FIG. 3E in the same manner ashas been described above with reference to FIG. 1F.

Referring now to FIGS. 4C and 4E, these Figures show the semiconductorbody 10 at stages corresponding to those shown respectively in FIGS. 3Cand 3E but modified as will now be described.

As illustrated in FIG. 4C, the gate insulting layer 17 of silicondioxide is provided in each trench 20 and has horizontal extensions 17 bin the same manner as shown in FIGS. 3B and 3C. However, instead ofdepositing a thin layer of silicon nitride 62′ as shown in FIG. 3C, athin layer of silicon dioxide 62″ is deposited on top of the mask 61 andin each window 61 c. Thus a U-shaped section layer of silicon dioxide isprovided in each window 61 c, as shown in FIG. 4C, having uprightportions 62A″ and a base portion 62B″ which provides a gate insulatingoverlayer on the gate material, the base portion 62B″ extending over thegate insulating layer horizontal extensions 17 b. The silicon dioxidelayer 62″ may suitably be provided by low pressure chemical vapourdeposition (LPCVD) of decomposed tetraethylorthosilicate (TEOS). Afiller 63 of polycrystalline silicon, or in this case possibly siliconnitride, is provided in the U-shaped section layers 62A″, 62B″. In thiscase, a single etching stage then removes the top layer 62″, the mask61, the upright portions 62A″ and part of the horizontal extensions 17 bwhich are all of the same material, silicon dioxide.

As illustrated in FIG. 4E, the p-type body regions 15 and the upper n+type regions are formed in the same manner as described above withreference to FIG. 3E, and then spacers 64 are formed with their verticalsurface against the filler 63. Each spacer 64 vertical surface isaligned with a surface of the filler 63 at the location of an innersurface of an upright portion 62A″ of the U-shaped section layer, thisupright portion having been removed. Again, the spacers 64 are used as amask to form the source regions 13 by etching as shown in FIG. 4E; andagain, the spacers 64 will then be reduced to expose the top surfaces ofthe source regions 13.

Referring now to FIG. 5E, this shows the semiconductor body 10 at astage corresponding to that shown in FIG. 1E but modified as will now bedescribed. A method is performed following precisely the stages asabove-described with reference to FIGS. 1A to 1D. Then the filler 63shown in FIG. 1D is removed by etching to leave the U-shaped sectionlayers 62A, 62B with space between the upright portions 62A. A layer ofdeposited silicon dioxide will then have a contoured upper surface (notshown) above the silicon nitride base portion 62B, the silicon nitrideupright portions 62A and the semiconductor body upper surface 10 a.Anisotropic etching of this contoured silicon dioxide layer forms thespacers 64 and at the same time forms further spacers 65 against innersurfaces of the upright portions 62A as shown in FIG. 5E, and thesefurther spacers 65 of silicon dioxide insulating material merge andcover the base portions 62B. When the spacers 64 are reduced in themanner described above with reference to FIG. 1F, the further spacers 65shown in FIG. 5E are also reduced but leave a further insulating layeron top of the gate insulating U-cup base 62B which has the advantage ofreducing gate-source capacitance in the transistor device.

Referring to FIGS. 6A to 6J, these Figures show the semiconductor body10 at successive stages in another example of a method which, inoverview, is as follows. A mask 61 of the first material, silicondioxide, has preceding U-shaped section layers 52A, 52B, 52C of thesecond material, silicon nitride, provided in its windows 61 a, seeFIGS. 6A and 6B. A central part of the base portion 52C of eachpreceding layer of silicon nitride is then removed to provide an etchwindow 52 a for a trench 20, see FIGS. 6C to 6G. The remainder of thepreceding layers of silicon nitride is then removed, and the mask 61 ofsilicon dioxide is then used for providing the U-shaped section layers62A, 62B which define steps for the spacers 64 used to form the sourceregions 13, see the stages shown in FIGS. 6H, 6I and 6J which correspondrespectively but are modified with respect to the stages shown in FIGS.3B, 3C and 3E. In this way, starting from one mask 61, a two-stageself-aligned process provides well-defined narrow trenches 20 and thenwell-defined source regions 13.

The successive stages of FIGS. 6A to 6J will now be described in detail.

FIG. 6A shows a monocrystalline silicon semiconductor body 10. A mask 61of first material, silicon dioxide is formed at a surface 10 a withwindows 61 a. The mask 61, having a typical thickness of 0.5 μm, and thewindow 61 a, having typical width 0.6 μm, are the same as shown in FIG.1A. Each window 61 a shown in FIG. 6A has a mid-point path coincidentwith a mid-point path of a trench which will be formed later, but inthis case the window 61 a is not used as an etch window to form thetrench.

As illustrated in FIG. 6B, a continuous thin layer 52 of a secondmaterial, in this example silicon nitride, is formed by deposition ontop of the first mask 61 and in each first window 61 a conformal to theshape of the window 61 a. The layer 52 has upright portions 52A, 52B onthe sidewalls of the first mask 61 and a base portion 52C on the surface10 a of the semiconductor body 10. In the typical example, the layer 52has a thickness of 0.05 μm.

As illustrated in FIG. 6C, a layer 53 of a third material, in thisexample polycrystalline silicon (or amorphous, or polycrystallinesilicon-germanium), is deposited on the layer 52 of silicon nitride ontop of the first mask 51 and in the first windows 61 a. In the typicalexample, the layer 53 may be 0.1 μm to 0.5 μm thick on top of the mask61. The layer 53 has a contoured upper surface with a dip in the regionof the window 61 a. The layer 53 is then anisotropically etched back toexpose the layer 52 of silicon nitride on top of the first mask 61 andto leave an intermediate mask of the third material in each first window61 a as two curved sidewall parts 53A, 53B as shown in FIG. 6D. Thesidewall parts 53A, 53B cover the upright portions 52A, 52B of the layerof silicon nitride and cover the base portion 52C of the layer ofsilicon nitride except at a central part where a second window will beformed. In the typical example the sidewall parts 53A, 53B each have awidth of 0.125 μm at their base and the uncovered width of the baseportion 52C is 0.25 μm.

As illustrated in FIG. 6E, the intermediate mask 53A, 53B in each firstwindow 61 a, is used to etch the central part of the base portion 52C ofthe layer of silicon nitride and form a second window 52 a. At the sametime, the silicon nitride layer 52 is removed from the top of the firstmask 51. As illustrated in FIG. 6F, the intermediate mask 53A, 53B isthen removed by etching to leave a pair of L-shaped parts of siliconnitride within each first window 61 a as two sidewall extensions to thefirst mask 61, each L-shaped part having an upright portion 52A, 52B andhaving a rectangular section base portion 52D, 52E with a top surfaceparallel to the semiconductor body surface 10 a and a side surfaceperpendicular to the semiconductor body surface. The two L-shapedsidewall extensions to the first mask 61 form a second mask on thesemiconductor body 10 with each second window 52 a in the second maskbeing formed within and smaller than a first window 61 a.

As illustrated in FIG. 6G a trench 20 is then formed by etching into thesemiconductor body 10 at each second window 52 a, preferably using ananisotropic plasma etch. The rectangular base portion 52D, 52E of eachL-shaped silicon nitride part ensures that there is no appreciablewidening of the second windows 52 a during trench etching, and so thetrenches 20 will be maintained narrow during etching in accordance withthe second windows 52 a. In the typical example the width of the trench20 is 0.25 μm and the depth of the trench 20 is 1.0 μm.

As illustrated in FIG. 6H, the remainder of the preceding U-shapedsection layer 52A, 52B, 52C of silicon nitride in each window 61 a, thatis to say the pair of L-shaped parts 52A, 52D and 52B, 52E, is thenremoved by etching to leave the first window 61 a in the first mask 61.

The method then proceeds with steps that are, in most respects, similarto those described above with reference to FIGS. 3B, 3C and 3E. Thus, asshown in FIG. 6H, the first window 61 a in the first, silicon dioxide,mask is already wider than the trench 20, the silicon dioxide gateinsulating layer 17 is formed with horizontal extensions 17 b on thesemiconductor body surface 10 a, and gate material 11 is provided to belevel with the top surface of the horizontal extensions 17 b. As shownin FIG. 61, a U-shaped section layer of silicon nitride is provided ineach window 61 a having upright portions 62A′ and a base portion 62B′,and polycrystalline silicon fillers 63 are provided. As shown in FIG.6J, the mask 61 is removed, p-type body regions 15 and upper n+ typeregions are provided, and silicon dioxide spacers 64 are formed and usedas an etching mask to form the source regions 13.

Advantages for a cellular trench-gate power transistor of the methoddescribed above with reference to FIGS. 6A to 6G, which is well adaptedfor producing narrow trenches, are as follows.

For comparatively low voltage vertical trench-gate power transistors,where the transistor cells are adapted to withstand a specifiedsource-drain voltage in the off-condition and where this specifiedvoltage is in the range up to about 50 volts, the channel resistance isthe predominant contribution to the specific on-resistance of thedevice. Where the transistor cells are configured in a two-dimensionallyrepetitive pattern, for example having a square cell geometry, narrowingthe trench-gate width for a given transistor cell pitch significantlyincreases the perimeter of the channel-accommodating region i.e.increases the channel width and hence reduces the channel resistance. Wehave found that where the cell pitch is 2 μm, a square cell device witha trench width of 0.25 μm has a 10 percent reduced specificon-resistance compared with a device having a trench width of 0.5 μm.Furthermore, we have found that for similar devices having a cell pitchin the range 1 μm to 3 μm, trenches having a width in the range of 0.1μm to 0.4 μm produce a reduction in specific on-resistance of up to 20%compared with devices having a trench width of 0.5 μm. The methoddescribed above is well adapted to producing trenches with thisindicated range of narrow widths. We envisage an aspect ratio of 4 ormore for the trenches of vertical trench-gate power transistors made inaccordance with this method, which for the range of trench widths justgiven may correspond to trenches having a depth in the range of 0.5 μmto 3 μm. We have found that for a given transistor cell pitch, narrowingthe trench-gate width reduces the gate-drain capacitance and hencereduces the RC delay time to a value which is comparable with that whichwould otherwise be achieved with a smaller cell pitch. Thus trenchwidths in the above-stated range of 0.1 μm to 0.4 μm provide, fortransistor cells having a cell pitch in the above-stated range of 1 μmto 3 μm, an RC delay time which is about the same as would otherwiseonly be achieved by a reduction of the cell pitch to about 0.5 μm. Alsofor a given transistor cell size within each surrounding trench-gatestructure, a narrower trench-gate allows a greater number of transistorcells to be accommodated within a given active area of the device with aconsequent reduction in the specific on-resistance of the device.

Variations and modifications of the above-described power transistorsand their methods of manufacture, within the scope of the presentinvention, include the following. In all cases where the spacers 64 areformed against the U-shaped section second layer uprights 62A, 62A′,this requires the second material for the second layer, given above assilicon nitride, to be different from the first material for the firstmask 61, given above as silicon dioxide. Other combinations of differentfirst and second materials are possible, for example the second materialbeing silicon dioxide and the first material being silicon nitride. Inthe case where the spacers 64 are formed against the filler 63, thefirst and second materials are the same, given above as silicon dioxide.In this case the first and second materials could instead both besilicon nitride, and the gate insulating layer 17, 17 b could also besilicon nitride. As shown in FIG. 1A, the mask 61 is formed on thesemiconductor body 10 which has the drain drift n-region 14 extending tothe top surface 10 a; and then as described above with reference to FIG.1D, the p body regions 15 and then the n+ regions 13 a for the sourceregions are provided by implantation and diffusion after forming thetrench-gate structures 20, 17, 11 and the U-shaped section layers 62A,62B with the filler 63. Another possibility is that, before forming themask 61 at the FIG. 1A stage the semiconductor body 10 could alreadyhave a p body region 15 formed by implantation or epitaxial depositionwith only the n+ region 13 a being formed at the stage of FIG. 1D; and afurther possibility is to provide both the p body regions 15 and the n+regions 13 a for the sources before forming the mask 61 at the FIG. 1Astage. In all the above-described examples the spacers 64 are used as amask for etching the upper n+ regions 13 a to form the source regions13. The spacers 64 could be used differently to form the source regions.Thus, the spacers 64 could be doped material, for example.polycrystalline silicon with n-type phosphorous or arsenic dopant, andthe source regions 13 could be formed by diffusing this dopant from thespacers 64 into an upper p-type body region 15. Another possibility isthat the spacers 64 themselves could form the source regions 13, thespacers in this case being either doped silicon or metal.

Further variations and modifications of the above-described powertransistors and their methods of manufacture, within the scope of thepresent invention, include the following. Instead of n-type conductivitysource and drain regions separated by a p-type conductivitychannel-accommodating region, the source and drain regions may be p-typewith the channel-accommodating region being n-type. Instead of thechannel-accommodating region being of the opposite conductivity type tothe source and drain regions in the usual type of device, thechannel-accommodating region may be of the same conductivity type as thesource and drain regions in an accumulation-mode device in which theconductive channel induced by the trench-gate in the on-state is formedby charge-carrier accumulation. At least some of the transistor cellsmay have a localised region of opposite conductivity type to the sourceand drain regions, the localised region extending into the semiconductorbody to the drain region and being separated from the trench-gate by thechannel-accommodating region. In the usual type of device, the localisedregions protect the cells against turning on of their in-built parasiticbipolar transistors.

Although Claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any Claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

The Applicants hereby give notice that new Claims may be formulated toany such features and/or combinations of such features during theprosecution of the present Application or of any further Applicationderived therefrom.

Thus, for example, as well as the invention set out in the followingclaims, there is also disclosed a method of manufacturing a trench-gatesemiconductor device comprising a semiconductor body 10 having aplurality of transistor cells, each transistor cell being surrounded bya trench-gate 11 comprising a trench 20 extending into the semiconductorbody with gate material 11 in the trench 20, and each transistor cellhaving source 13 and drain 14 regions which are separated by achannel-accommodating region 15 adjacent to the trench-gate 11, whereinthe method includes the steps of:

(a) forming at a surface 10 a of the semiconductor body 10 a first mask61 of a first material having first windows 61 a, each first window 61 ahaving a mid-point path coincident with a mid-point path of a saidtrench 20 which will be formed later;

(b) forming on the semiconductor body 10 a second mask 52A, 52D and 52B,52E having second windows 52 a, each second window 52 a being formedwithin and smaller than a said first window 61 a by providing twosidewall extensions to the first mask 61 in the first window 61 a; and

(c) forming said trenches 20 by etching into the semiconductor body 10at the second windows 62 a;

wherein the method has the steps of:

(d) providing in each first window 61 a a continuous layer of a secondmaterial 52 from which the second mask will be formed, the layer ofsecond material having upright portions 52A, 52B on the sidewalls of thefirst mask 61 and a base portion 52 c on the surface 10 a of thesemiconductor body;

(e) forming an intermediate mask 53A, 53B of a third material 53 in eachfirst window 61 a covering the upright portions 52A, 52B of the layer ofsecond material 52 and covering the base portion 52C of the layer ofsecond material except where the second window 52 a will be formed;

(f) using the intermediate mask 53A, 53B in each first window 61 a toetch the base portion 52C of said layer of second material and form saidsecond window 52 a; and

(g) removing the intermediate mask 53A, 53B to leave a pair of L-shapedparts 52A, 52D and 52B, 52E of said second material 52 within each firstwindow 61 a as said two sidewall extensions to the first mask, eachL-shaped part having a rectangular section base portion 52D, 52E with atop surface parallel to the semiconductor body surface 10 a and a sidesurface perpendicular to the semiconductor body surface 10 a, and thencarrying out step (c) to form said trenches 20.

What is claimed is:
 1. A method of manufacturing a vertical powertransistor trench-gate semiconductor device having a plurality oftransistor cells, each transistor cell being surrounded by a trench-gatestructure comprising a trench extending into a semiconductor body withgate material in the trench and a gate insulating layer between thetrench and the gate material, and each transistor cell having an annularsource region adjacent an upper part of the trench-gate structure andseparated from a drain region by a channel-accommodating body regionadjacent the trench-gate structure, wherein the method includes formingthe source regions so as to be self-aligned to the trench-gatestructures, characterised in that the method includes the steps of: (a)forming on a surface of the semiconductor body a first mask of a firstmaterial with first windows, each said first window having a mid-pointpath coincident with a mid-point path of the location of a said trench;(b) providing in each first window a U-shaped section layer of aninsulating second material, the layers of second material being providedafter the trench-gate structures are formed, each layer of secondmaterial having upright portions on the side walls of the first windowand a base portion which provides a gate insulating overlayer on thegate material of a said trench-gate structure; (c) removing the firstmask and then forming spacers, each spacer having a vertical surfacewhich is aligned with the location of a surface of a said uprightportion of the layer of second material and each spacer having ahorizontal base surface; (d) using the spacers to form the annularsource regions with the lateral extent of the source regions from thetrench-gate structures being determined by the lateral extent of thebase surface of the spacers; and (e) providing a source electrode tocontact the source regions and the body regions adjacent the sourceregions.
 2. A method as claimed in claim 1, wherein the trenches areetched into the semiconductor body at etch windows in a mask of saidfirst material, and wherein these etch windows are narrowed by upwardextensions of the gate insulating layers which are of said firstmaterial, the narrowed etch windows forming the first windows in thefirst mask, wherein the first and second materials are such thatremoving the first mask by etching does not remove said upright portionsof second material, and wherein each said spacer vertical surface isaligned with an outer surface of a said upright portion of secondmaterial.
 3. A method as claimed in claim 1, wherein the trenches areetched into the semiconductor body at etch windows in a mask of saidfirst material, wherein these etch windows are then widened to form thefirst windows in the first mask, wherein the gate insulating layers arethen provided in the trenches and have horizontal extensions on thesurface of the semiconductor body within the first windows, wherein thegate material is then provided to complete the trench-gate structures,wherein said base portions of second material extend over the gateinsulating layer horizontal extensions, and wherein at least part of thegate insulating layer horizontal extensions remain when the first maskis removed.
 4. A method as claimed in claim 3, wherein the first andsecond materials are such that removing the first mask by etching doesnot remove said upright portions of second material, and wherein eachsaid spacer vertical surface is aligned with an outer surface of a saidupright portion of second material.
 5. A method as claimed in claim 1,wherein, before step (b), a mask of said first material is formed on thesurface of the semiconductor body with windows which each have amid-point path coincident with a mid-point path of the location of asaid trench, a preceding U-shaped section layer of the second materialis then provided in each window, each said preceding layer of secondmaterial having upright portions on the sidewalls of the window and abase portion on the surface of the semiconductor body, a central part ofthe base portion of each preceding layer of second material is thenremoved to provide an etch window in this base portion, the trenches areetched into the semiconductor body at these etch windows, and theremainder of the preceding layers of second material is then removed. 6.A method as claimed in claim 5, wherein, after the remainder of thepreceding layers of second material is removed, the windows in the maskof first material provide said first windows in said first mask.
 7. Amethod as claimed in claim 5, wherein the first and second materials aresuch that removing the first mask by etching does not remove saidupright portions of second material, and wherein each said spacervertical surface is aligned with an outer surface of a said uprightportion of second material.
 8. A method as claimed in claim 2, whereinin step (b) the U-shaped section layers of second material are filledwith a third material, and wherein in step (c) the spacers are formedwith the third material present and covering the base portions of theU-shaped section layers of second material.
 9. A method as claimed inclaim 2, wherein in step (b) the U-shaped section layers of secondmaterial are filled with a third material, and wherein in step (c) thethird material is removed before forming the spacers of an insulatingmaterial such that, at the same time as the spacers are formed, furtherspacers are formed against inner surfaces of the upright portions andthese further spacers of insulating material merge and cover the baseportions of the U-shaped section layers of second material.
 10. A methodas claimed in claim 2, wherein the semiconductor body is monocrystallinesilicon, the gate insulating layers are silicon dioxide, the firstmaterial is silicon dioxide, and the second material is silicon nitride.11. A method as claimed in claim 3, wherein the U-shaped section layersof second material are filled with a third material, and wherein thefirst and second materials are such that removing the first mask byetching also removes the upright portions of the layers of secondmaterial so that each said spacer vertical surface is aligned with asurface of the third material at the location of an inner surface of asaid upright portion of the layers of second material.
 12. A method asclaimed in claim 11, wherein the semiconductor body is monocrystallinesilicon, the gate insulating layers are silicon dioxide, and the firstand second materials are both silicon dioxide.
 13. A method as claimedin claim 1, wherein regions of one conductivity type suitable for theannular source regions are present in upper parts of the semiconductorbody surrounded by the U-shaped section layers of second material beforeforming the spacers, and wherein the annular source regions are formedby etching the regions of one conductivity type using the spacers as amask.
 14. A method as claimed in claim 13, wherein said etching to formthe source regions exposes side surfaces of the source regions, andwherein the spacers are then etched to expose top surfaces of the sourceregions, whereby in step (e) the source electrode contacts the sourceregion exposed side surfaces and the source region exposed top surfaces.15. A method as claimed in claim 13, wherein the regions of oneconductivity type are formed by dopant implantation and diffusion afterremoving the first mask.